1. Field of the Invention
The present invention relates to a layered chip package that includes a plurality of semiconductor chips stacked, a method of manufacturing the same, and a substructure for use in manufacturing the layered chip package.
2. Description of the Related Art
In recent years, lighter weight and higher performance have been demanded of portable devices typified by cellular phones and notebook personal computers. Accordingly, there has been a need for higher integration of electronic components for use in the portable devices. With the development of image- and video-related equipment such as digital cameras and video recorders, semiconductor memories of larger capacity and higher integration have also been demanded.
As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing quick circuit operation and a reduced stray capacitance of the wiring, as well as the advantage of allowing higher integration.
Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. The wire bonding method stacks a plurality of chips on a substrate and connects a plurality of electrodes formed on each chip to external connecting terminals formed on the substrate by wire bonding. The through electrode method forms a plurality of through electrodes in each of chips to be stacked and wires the chips together by using the through electrodes.
U.S. Patent Application Publication No. US 2008/0179728 A1 describes a laminated memory formed using the through electrode method.
JP-A-2003-163324 describes a three-dimensional laminated semiconductor device in which a plurality of chips stacked are wired by using wiring plugs that are similar to through electrodes. The three-dimensional laminated semiconductor device includes a stack of a plurality of unit semiconductor devices. Each single unit semiconductor device includes a semiconductor chip having a chip electrode, a wiring pattern, molding resin, and wiring plugs. The chip electrode is mounted on one surface of the wiring pattern. The molding resin covers the semiconductor chip and the wiring pattern. The wiring plugs penetrate the molding resin outside the semiconductor chip. The wiring plugs each have one end in contact with the one surface of the wiring pattern, and the other end exposed from the molding resin. The other surface of the wiring pattern is exposed in the surface of the molding resin. In the three-dimensional laminated semiconductor device, the wiring plugs of the lower one of two unit semiconductor devices are put into contact with the exposed surface of the wiring pattern of the upper one of the two unit semiconductor devices, whereby the plurality of semiconductor chips are wired together.
The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between the wires, and the problem that the high resistances of the wires hamper quick circuit operation.
The through electrode method is free from the above-mentioned problems of the wire bonding method. Unfortunately, however, the conventional through electrode method requires a large number of steps for forming the through electrodes in chips, and consequently increases the cost for the layered chip package. According to the conventional through electrode method, forming the through electrodes in chips requires a series of steps as follows: forming a plurality of holes for the plurality of through electrodes in a wafer that is to be cut later into a plurality of chips; forming an insulating layer and a seed layer in the plurality of holes and on the top surface of the wafer; filling the plurality of holes with metal such as Cu by plating to form the through electrodes; and removing unwanted portions of the seed layer.
As with the foregoing problem with the conventional through electrode method, the three-dimensional laminated semiconductor device described in JP-A-2003-163324 requires a large number of steps for forming the wiring plugs, which leads to the problem of increased cost.